UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 207

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3
(1) Processor clock control register (PCC)
Note The CLS bit is a read-only bit.
Caution Do not change the CPU clock (by using the CK2 to CK0 bits of the PCC register) while
Remark
Control Registers
The processor clock control register (PCC) is a special register. Data can be written to it only in combination of
specific sequences (refer to 3.4.8 Special registers).
This register can be read or written in 8-bit or 1-bit units. The CLS bit is a read-only bit.
CLKOUT is being output.
X: Don’t care.
After reset:
PCC
• Even if the MCK bit is set to 1 while the system is operating with the main clock as
• When the main clock is stopped and the device is operating on the subclock, clear
MFRC
MCK
FRC
the CPU clock, the operation of the main system clock does not stop. It stops after
the CPU clock has been changed to the subclock.
the MCK bit to 0 and wait until the oscillation stabilization time has been secured
by the program before switching back to the main clock.
03H
FRC
CLS
CK3
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
CHAPTER 6 CLOCK GENERATION FUNCTION
Used
Not used
Operating
Stopped
Used
Not used
Main clock operation
Subclock operation
R/W
MCK
CK2
<6>
X
0
0
0
0
1
1
1
Address:
User’s Manual U15905EJ2V1UD
MFRC
Selects internal feedback resistor of main clock
CK1
Selects internal feedback resistor of subclock
0
0
1
1
0
0
1
X
FFFFF828H
CLS
Status of CPU clock (f
CK0
<4>
Operation of main clock
X
X
0
1
0
1
0
1
Note
f
f
f
f
f
f
Setting prohibited
f
XX
XX
XX
XX
XX
XX
XT
CK3
<3>
/2
/4
/8
/16
/32
(subclock:
Selects clock
CPU
CK2
32.768 kHz)
)
(f
CK1
CLK
/f
CPU
)
CK0
205