UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 206

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(1) Main clock oscillator
(2) Subclock oscillator
(3) Main clock resonator stop control
(4) Prescaler 1
(5) Prescaler 2
(6) Prescaler 3
(7) Watchdog timer clock control
This circuit oscillates the following frequency (f
• 2 to 20 MHz (at 2.2 to 2.7 V operation)
This circuit oscillates a frequency of 32.768 kHz (f
This circuit generates a control signal that stops oscillation of the main clock resonator.
It stops the oscillation of the main clock resonator in the software STOP mode or when the MCK bit = 1 (valid
only when the CLS bit = 1).
This circuit generates the clock (f
The clock is supplied to the following blocks:
TM0 to TM5, CSI0 to CSI4, UART0, UART1, I
This circuit divides the main clock (f
The clock generated by prescaler 2 (f
clock (f
f
CLKOUT pin.
This circuit divides the clock (f
supplies it to the RTC and ADC.
For details, refer to 6.5 Prescaler 3.
This circuit generates the clock (f
The watchdog timer is used alternately as the oscillation stabilization timer, so the source clock is automatically
switched according to the operation status shown below.
• From software STOP mode or RESET pin input to when oscillation stabilization time has been counted: f
• Other than above: f
CLK
is the clock that is supplied to the CPU, INTC, DMAC, and ROMC blocks, and can be output from the
CLK
).
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CHAPTER 6 CLOCK GENERATION FUNCTION
X
) generated by the main resonator to a specific frequency (32.768 kHz) and
XX
XW
XX
) to be supplied to the watchdog timer.
to f
).
XX
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User’s Manual U15905EJ2V1UD
to f
/512) to be supplied to the internal peripheral functions.
XX
2
/32) is supplied to the selector that generates the internal system
C, ADC, DAC
X
):
XT
).
X