UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 394

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.11 Arbitration
1
differs. This kind of operation is called arbitration.
set via the timing by which the arbitration loss occurred, and the SCL and SDA lines are both set to high impedance,
which releases the bus.
stop condition is detected, etc.) and the ALD = 1 setting that has been made by software.
392
Note
Transfer lines
When several master devices simultaneously output a start condition (when STT is set to 1 before STD is set to
When one of the master devices loses in arbitration, an arbitration loss flag (ALD) in the IIC status register (IICS) is
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
For details of interrupt request timing, see 15.6 I
Note STD: Bit 1 of IIC status register (IICS)
Master 1
Master 2
), communication among the master devices is performed as the number of clocks is adjusted until the data
STT: Bit 1 of IIC control register (IICC)
SDA
SDA
SDA
SCL
SCL
SCL
Figure 15-13. Arbitration Timing Example
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
2
C Interrupt Request (INTIIC).
2
C BUS
Master 1 loses arbitration
Hi-Z
Hi-Z