UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 426

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.11.1 Interrupt factors
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(10) When DMA transfer is complete, update is performed in the order of clearing the Enn bit of the DCHCn register
(11) When the TCn bit of the DCHCn register is confirmed to be set to 1 after reading the bit, read the TCn bit three
(12) The shortest interval for requesting DMA transfer to the same channel varies depending on the bus wait setting
(13) Do not apply start factors (hardware trigger, software trigger) to the same channel at the same time. If two
(14) Before starting DMA transfer by manipulating the STGn bit (setting the STGn bit of the DCHCn register to 1),
(15) When performing DMA transfer whose target is the internal RAM while an instruction from the internal RAM is
DMA transfer is interrupted if a bus hold is issued.
If the factor (bus hold) interrupting DMA transfer disappears, DMA transfer promptly restarts.
(b) To repetitively set the INITn bit until DMA is successfully initialized
to 0 and then setting the TCn bit to 1. Therefore, the status of Enn bit = TCn bit = 0 may be read depending on
the timing of reading the DCHCn register.
more times.
during the read cycle/write cycle, activation status of other channels, and external bus hold request.
Input a sufficiently long interval for a transfer request to the same channel so that the bus cycle can be
completed in the system.
start factors are generated for one channel, only one or the other factor is valid. Therefore, the entire system
may not operate normally.
perform a second or subsequent transfer after making sure that the previous DMA transfer has been
completed (check the DBCn register or the TCn bit of the DCHCn register).
in progress, do not include bit manipulation instructions and misalign access in the program that executes
instructions from the internal RAM.
<1> Clear the Enn bit of the DCHCn register of the channel to be initialized to 0.
<2> Clear the Enn bit of the DCHCn register of the channel to be initialized to 0.
<3> Copy the number of initial transfers of the channel to be initialized to a general-purpose register.
<4> Set the INITn bit of the channel to be initialized to 1.
<5> Read the value of the DMA transfer count register (DBCn) of the channel to be initialized and
Caution 2. Do not configure programs that expect the TCn bit of the DCHCn register to be
If the transfer target of the channel to be initialized (transfer source or transfer destination) is the
internal RAM, clear the Enn bit of the DCHCn register to 0 once again.
compare it with the value copied in step <3>. If these values do not match, repeat steps <4> and
<5>.
set to 1 by other than the above processing (the TCn bit of the DCHCn register is
cleared to 0 after a read, so the bit is cleared when the instruction in <5> has
been executed).
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U15905EJ2V1UD