UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 216

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

214
(1) Timers 0 and 1 (TM0 and TM1)
TM0
TM1
TMn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being used
for cycle measurement, TMn can be used for pulse output (n = 0, 1).
TMn is read-only, in 16-bit units.
Cautions 1. The TMn register can only be read.
TMn performs the count-up operations of an internal count clock or external count clock. Timer start and stop
are controlled by the TMCEn bit of timer mode control register n0 (TMCn0) (n = 0, 1).
The internal or external count clock is selected by the ETIn bit of timer mode control register n1 (TMCn1) (n =
0, 1).
(a) Selection of the external count clock
(b) Selection of the internal count clock
TMn operates as an event counter.
When the ETIn bit of timer mode control register n1 (TMCn1) is set (1), TMn counts the valid edges of the
external clock input (TIn), synchronized with the internal count clock. The valid edge is specified by valid
edge select register n (SESn) (n = 0, 1).
Caution When the INTPn0/TIn/TCLRn pin is used as TIn (external clock input pin), disable the
TMn operates as a free-running timer.
When the internal clock is specified as the count clock by timer mode control register n1 (TMCn1), TMn is
counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCn0 register (n = 0, 1).
Division by the prescaler can be selected for the count clock from among f
f
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an
overflow by setting the OSTn bit of the TMCn1 register to 1.
Caution The count clock cannot be changed while the timer is operating.
XX
15
/64, f
14
2. If the TMCAEn bit of the TMCn0 register is cleared (0), a reset is performed
XX
/128, and f
operation is undefined.
asynchronously.
13
INTPn0 interrupt and set CCn0 to compare mode (n = 0, 1).
12
11 10
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
XX
/256 by the TMCn0 register (f
9
8
User’s Manual U15905EJ2V1UD
7
6
5
4
XX
: Internal system clock).
If the TMn register is written, the subsequent
3
2
1
0
FFFFF600H
FFFFF610H
XX
Address
/2, f
XX
/4, f
XX
/8, f
After reset
XX
0000H
0000H
/16, f
XX
/32,