UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 400

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.14 Cautions
released) to a master device communication mode, first generate a stop condition to release the bus, then perform
master device communication.
been released (when a stop condition has not been detected).
398
After a reset, when changing from a mode in which no stop condition has been detected (the bus has not been
When using multiple masters, it is not possible to perform master device communication when the bus has not
Use the following sequence for generating a stop condition.
<1> Set the IIC clock selection register (IICCL).
<2> Set bit 7 (IICE) of the IIC control register (IICC).
<3> Set bit 0 of IICC.
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
2
C BUS