UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 393

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.8 Address Match Detection Method
slave address.
local address has been set to the slave address register (SVA) and when the address set to SVA matches the slave
address sent by the master device, or when an extension code has been received.
15.9 Error Detection
register (IIC) of the transmitting device, so the IIC data prior to transmission can be compared with the transmitted IIC
data to enable detection of transmission errors.
compared data values do not match.
15.10 Extension Code
When in I
Address match detection is performed automatically by hardware. An interrupt request (INTIIC) occurs when a
In I
(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXC) is set for
(2) If 11110xx0 is set to SVA by a 10-bit address transfer and 11110xx0 is transferred from the master device, the
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
2
C bus mode, the status of the serial data bus (SDA) during data transmission is captured by the IIC shift
extension code reception and an interrupt request (INTIIC) is issued at the falling edge of the eighth clock.
The local address stored in the slave address register (SVA) is not affected.
results are as follows. Note that the INTIIC signal occurs at the falling edge of the eighth clock.
Higher four bits of data match: EXC = 1
Seven bits of data match: COI = 1
Note EXC: Bit 5 of IIC status register (IICS)
code, such processing is performed by software.
For example, when operation as a slave is not desired after the extension code is received, set bit 6 (LREL) of
the IIC control register (IICC) to 1 and the CPU will enter the next communication wait state.
0000
0000
0000
0000
1111
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding
COI: Bit 4 of IIC status register (IICS)
Slave Address
000
000
001
010
0xx
Table 15-4. Extension Code Bit Definitions
R/W Bit
Note
0
1
×
×
×
User’s Manual U15905EJ2V1UD
Note
CHAPTER 15 I
General call address
Start byte
CBUS address
Address that is reserved for different bus format
10-bit slave address specification
A transmission error is judged as having occurred when the
2
C BUS
Description
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