UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 307

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

• To overwrite the ISRM bit, first clear (0) the RXEn bit.
• To overwrite the SL bit, first clear (0) the TXEn bit.
• Since reception is always performed with a stop bit length of 1, the SL bit setting
• To overwrite the CL bit, first clear (0) the TXEn and RXEn bits.
ISRMn
CLn
SLn
does not affect receive operations.
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
0
1
0
1
0
1
7 bits
8 bits
1 bit
2 bits
Generate a reception error interrupt request (INTSREn) as an interrupt
when an error occurs.
In this case, no reception completion interrupt request (INTSRn) is
generated.
Generate a reception completion interrupt request (INTSRn) as an
interrupt when an error occurs.
In this case, no reception error interrupt request (INTSREn) is
generated.
Enables/disables generation of reception completion interrupt requests
Specifies character length of 1 frame of transmit/receive data
User’s Manual U15905EJ2V1UD
Specifies stop bit length of transmit data
when an error occurs
(3/3)
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