UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 423

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.8 DMA Channel Priorities
switched.
16.9 DMA Transfer Start Factors
16.10 DMA Transfer End
16.10.1 DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
16.10.2 Terminal count output upon DMA transfer end
The DMA channel priorities are fixed as follows.
These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never
There are two types of DMA transfer start factors, as shown below.
(1) Request from software
(2) Request from on-chip peripheral I/O
When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
The terminal count signal becomes active for one clock during the last DMA transfer cycle.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3).
• STGn bit = 1
• Enn bit = 1
• TCn bit = 0
If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued
from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3).
• Enn bit = 1
• TCn bit = 0
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U15905EJ2V1UD
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