UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 28

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1.6.2
26
(1) CPU
(2) Bus control unit (BCU)
(3) ROM
(4) RAM
(5) Interrupt controller (INTC)
(6) Clock generator (CG)
(7) Timer/counter
(8) Real-time counter (for watch)
(9) Watchdog timer
The CPU can execute almost all instruction processing, such as address calculation, arithmetic logic
operations, and data transfer, with 1 clock, using a 5-stage pipeline.
The CPU has dedicated hardware units such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32
bits) to speed up complicated instruction processing.
The BCU starts the required external bus cycles in accordance with the physical address obtained by the CPU.
If the CPU does not request the start of a bus cycle when an instruction is fetched from the external memory
area, the BCU generates a prefetch address and prefetches an instruction code. The prefetched instruction
code is loaded to the internal instruction queue.
This is a 256 KB or 128 KB mask ROM or flash memory mapped to addresses 0000000H to 003FFFFH or
0000000H to 001FFFFH. The CPU can access the ROM with 1 clock when an instruction is fetched.
This is a 16 KB or 8 KB RAM mapped to addresses 3FFB000H to 3FFEFFFH or 3FFD000H to 3FFEFFFH. It
can be accessed by the CPU with 1 clock when data is accessed.
The INTC processes hardware interrupt requests (NMI, INTP0 to INTP6) from the internal peripheral hardware
and external sources. Eight levels of priority can be specified for these interrupt requests. Multiple interrupts
can also be processed.
Two oscillators, one for the main clock (f
clocks (f
operation clock (f
A two-channel 16-bit timer/event counter and four-channel 8-bit timer/event counter are available, enabling
pulse interval and frequency measurement and programmable pulse output.
Two 8-bit timer/event counter channels can be connected in cascade and used as a 16-bit timer.
This counter counts the reference time (1 second) for the watch count from the subclock (32.768 kHz) or main
clock. It can also be used as an interval timer that operates with the main clock. Dedicated hardware counters
for counting weeks, days, hours, minutes, and seconds, are provided, and up to 4095 weeks can be counted.
A watchdog timer that detects program hang-up and system errors is provided.
This watchdog timer can also be used as an interval timer.
When used as a watchdog timer, a non-maskable interrupt request (INTWDT) is generated if the watchdog
timer overflows. When used as an interval timer, a maskable interrupt request is generated when the timer
overflows.
Internal units
X
, f
X
/2, f
X
CPU
/4, f
). The subclock can be selected only as the operation clock for the real-time counter.
X
/8, f
X
/16, f
X
/32, and f
CHAPTER 1 INTRODUCTION
User’s Manual U15905EJ2V1UD
X
) and the other for the subclock (f
XT
) can be generated, of which one is supplied to the CPU as the
XT
), are provided. Seven types of