UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 217

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Capture/compare registers n0 and n1 (CCn0 and CCn1) (n = 0, 1)
Remark
CC0n
CC1n
The conditions when the TMn register becomes 0000H are shown below.
(a) Asynchronous reset
(b) Synchronous reset
These capture/compare registers (n0 and n1) are 16-bit registers.
They can be used as capture registers or compare registers according to the CMSn0 and CMSn1 bit
specifications of timer mode control register n1 (TMCn1) (n = 0, 1).
These registers can be read or written in 16-bit units. (However, write operations can only be performed in
compare mode.)
These registers are cleared to 0000H after reset.
(a) Setting these registers as capture registers (CMSn0 and CMSn1 of TMCn1 = 0)
• TMCAEn bit of TMCn0 register = 0
• After reset
• TMCEn bit of TMCn0 register = 0
• The CCn0 register is used as a compare register, and the TMn and CCn0 registers match when clearing
When these registers are set as capture registers, the valid edges of the corresponding external interrupt
signals INTPn0 and INTPn1 are detected as capture triggers. The timer TMn is synchronized with the
capture trigger, and the value of TMn is latched in the CCn0 and CCn1 registers (capture operation).
The valid edge of the INTPn0 pin is specified (rising, falling, or both rising and falling edges) according to
the IESn01 and IESn00 bits of the SESn register, and the valid edge of the INTPn1 pin is specified
according to the IESn11 and IESn10 bits of the SESn register (n = 0, 1).
The capture operation is performed asynchronously to the count clock. The latched value is held in the
capture register until another capture operation is performed (n = 0, 1).
When the TMCAEn bit of timer mode control register n0 (TMCn0) is 0, 0000H is read (n = 0, 1).
If these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of
signals INTPn0 and INTPn1 (n = 0, 1).
Caution If the capture operation conflicts with the timing of disabling the TMn register from
the TMn register is enabled (CCLRn bit of the TMCn1 register = 1)
n = 0, 1
15
14
counting (when the TMCEn bit of the TMCn0 register = 0), the captured data becomes
undefined. In addition, the INTCCn0 and INTCCn1 interrupts do not occur (n = 0, 1).
13
12
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
11 10
9
8
User’s Manual U15905EJ2V1UD
7
6
5
4
3
2
1
0
FFFFF602H,
FFFFF604H
FFFFF612H,
FFFFF614H
Address
After reset
0000H
0000H
215