UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 49
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(13) PDL0 to PDL15 (Port DL) … 3-state I/O
(14) RESET (Reset) … Input
(15) X1, X2 (Crystal for main clock)
(16) XT1, XT2 (Crystal for subclock)
(17) AV
(18) AV
(19) AV
(20) AV
(a) Port mode
(b) Control mode
Port DL is a 16-bit I/O port that can be set to the input or output mode in 1-bit units.
Besides functioning as I/O port pins, PDL0 to PDL15 also operate a time-division address/data bus (AD0 to
AD15) when the memory is externally expanded. Each bit of the port can be individually set to the port or
control mode.
In addition, the PDL5 pin of the
pin when the flash memory is programmed (when a high level is input to FLMD0). At this time, be sure to
input a low level to the FLMD1 pin.
The RESET signal is input asynchronously. If a signal having a specific low-level width is input to this pin,
regardless of the operation clock, the system is reset as a priority over all other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP) as well as for normal
initialization/starting.
Connect an oscillator for system clock generation to these pins.
Connect an oscillator for subclock generation to these pins.
This pin supplies positive power to the A/D converter and alternate-function port pins.
This is a ground pin for the A/D converter and alternate-function port pins.
This pin supplies a reference voltage to the A/D converter.
This pin supplies a reference voltage to the D/A converter.
DD
SS
REF0
REF1
PDL0 to PDL15 can be set to the input or output mode in 1-bit units by using port mode register DL
(PMDL).
(i) AD0 to AD15 (address/data bus 0 to 15) … 3-state I/O
(Analog V
(Analog V
(Analog reference voltage) … Input
(Analog reference voltage) … Input
This is a multiplexed address/data bus that is used to access an external device. In the multiplexed
bus mode, it outputs an address or inputs/outputs data. In the separate bus mode, the bus inputs or
outputs data.
SS
DD
)
)
µ
PD70F3201, 70F3201Y, 70F3204, and 70F3204Y functions as the FLMD1
CHAPTER 2 PIN FUNCTIONS
User’s Manual U15905EJ2V1UD
47
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