UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 416

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
only. If bit 1 or 2 is read, the read value is always 0.)
414
These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3).
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write-
Notes 1. The TCn bit is read-only.
Caution Before generating a DMA transfer request by software, make sure that the TCn bit is set to 1
Remark
2. The INITn and STGn bits are write-only.
and then clear the TCn bit to 0.
If the completion of DMA transfer and the bit manipulation instruction for the DCHCn register conflict,
the Enn bit may not be cleared.
(n = 0 to 3)
DCHCn
After reset:
TCn
It is set to 1 when DMA transfer ends and cleared (to 0) when it is read.
Set the INIT bit to 1 when the Enn bit is 0.
This bit is cleared to 0 when DMA transfer ends.
STGn
INITn
00H
TCn
Enn
<7>
0
1
0
1
Note 1
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
DMA transfer had not ended.
DMA transfer had ended.
When changing the DDAnH, DDAnL, DSAnL, DSAnH, or DBCn register
before the number of transfers set by DBCn has finished,
set this bit to 1 to initialize DMA.
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
DMA transfer disabled
DMA transfer enabled
R/W
0
6
User’s Manual U15905EJ2V1UD
Address:
5
0
DMA channel n is to be enabled or disabled
Status flag indicates whether DMA transfer
through DMA channel n has ended or not
Setting of whether DMA transfer through
DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
4
0
3
0
INITn
<2>
Note 2
STGn
<1>
Note 2
Enn
<0>