UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 548
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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B.2 Instruction Set (In Alphabetical Order)
546
ADD
ADDI
AND
ANDI
Bcond
BSH
BSW
CALLT
CLR1
CMOV
CMP
CTRET
DBRET
Mnemonic
reg1,reg2
imm5,reg2
imm16,reg1,reg2
imm16,reg1,reg2
disp9
imm6
bit#3, disp16[reg1]
reg2,[reg1]
cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i
cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR
reg1,reg2
imm5,reg2
reg1,reg2
reg2,reg3
reg2,reg3
Operand
r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1]
r r r r r 0 1 0 0 1 0 i i i i i
r r rr r1 10 00 0 RRRRR
i i i i i i i i i i i i i i i i
r r rr r0 01 01 0 RRRRR GR[reg2]←GR[reg2]AND GR[reg1]
r r rr r1 10 11 0 RRRRR
i i i i i i i i i i i i i i i i
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000010
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000000
0 0 0 0 0 0 1 0 0 0 i i i i i i
10bbb111110RRRRR
dddddddddddddddd
r r rr r1 11 11 1 RRRRR
0000000011100100
wwwww011000cccc0
wwwww011001cccc0
r r rr r0 01 11 1 RRRRR result←GR[reg2]–GR[reg1]
r r r r r 0 1 0 0 1 1 i i i i i
0000011111100000
0000000101000100
0000011111100000
0000000101000110
ddddd1011dddcccc
Opcode
APPENDIX B INSTRUCTION SET LIST
Note 1
User’s Manual U15905EJ2V1UD
GR[reg2]←GR[reg2]+sign-extend(imm5)
GR[reg2]←GR[reg1]+sign-extend(imm16)
GR[reg2]←GR[reg1]AND zero-extend(imm16)
if conditions are satisfied
then PC←PC+sign-extend(disp9)
GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
[reg2] (23 : 16) ll GR[reg2] (31 : 24)
CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
adr←GR[reg1]+sign-extend(disp16)
Z flag←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
adr←GR[reg1]
Z flag←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
if conditions are satisfied
then GR[reg3]←sign-extend(imm5)
else GR[reg3]←GR[reg2]
if conditions are satisfied
then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
result←GR[reg2]–sign-extend(imm5)
PC←CTPC
PSW←CTPSW
PC←DBPC
PSW←DBPSW
Operation
When conditions
are satisfied
When conditions
are not satisfied
Note 2
Note 3
Note 3
1
1
1
1
1
1
2
1
1
4
3
3
1
1
1
1
3
3
Execution
i
Clock
Note 2
Note 3
Note 3
1
3
3
1
1
1
1
1
2
1
1
4
3
3
1
1
1
1
r
Note 2
Note 3
Note 3
3
3
1
1
1
1
1
2
1
1
1
4
3
3
1
1
1
1
l
CY OV S
R
R
×
×
×
×
×
×
×
R
R
×
×
×
0
0
0
0
×
×
Flags
R
R
×
×
×
×
×
×
×
×
×
R
R
Z SAT
×
×
×
×
×
×
×
×
×
×
×
(1/6)
R
R
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