UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 203

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

AD7 to AD0
CS3 to CS0
WR1, WR0
Note This idle state (TI) does not depend on the BCC register settings.
Remark
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded.
A23 to A0
CLKOUT
HLDRQ
HLDAK
AD15 to AD0
CS3 to CS0
Figure 5-14. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access)
A23 to A0
2. TAHW (address hold wait): Image of low-level width of T1 state expanded.
3. The broken lines indicate high impedance.
The broken lines indicate high impedance.
CLKOUT
11
ASTB
WAIT
T1
RD
A1
10
Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write)
T2
D1
T1
11
T1
A1
D1
CHAPTER 5 BUS CONTROL FUNCTION
A2
T2
10
T2
D2
User’s Manual U15905EJ2V1UD
Undefined
11
1111
AD15 to AD0
TI
CS3 to CS0
íç
A23 to A0
CLKOUT
ASTB
WAIT
TH
RD
TH
TASW
TH
T1
TH
A1
TAHW
Undefined
D1
1111
TI
íç
11
T2
T1
A3
10
T2
D3
11
201