UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 372

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

370
(6) Wait signal (WAIT)
The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCL pin to low level notifies the communication partner of the wait status. When the wait status
has been canceled for both the master and slave devices, the next data transfer can begin.
Transfer lines
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
Slave
ACKE
SDA
SCL
SCL
SCL
IIC
IIC
(Master: transmission, slave: reception, and ACKE = 1)
H
D2
6
6
Figure 15-12. Wait Signal (1/2)
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
D0
8
8
9
ACK
2
C BUS
9
FFH is written to IIC or WREL is set to 1.
Wait after output
of ninth clock.
IIC data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3