UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 259

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4.7
connection.
mode control registers 3 and 5 (TMC3 and TMC5) to 1.
compare registers 23 and 45 (CR23 and CR45).
TM5.
The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade
The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TCM54 bits of 8-bit timer
8-bit timer/event counter n outputs a square wave of any frequency using the interval preset in 16-bit timer
In the following description, TM2 and TM3 are used. Read TM2 and TM3 as TM4 and TM5 when using TM4 and
Setting method (when TM2 and TM3 are connected in cascade)
<1> Set each register.
<2> Set the TMCE3 bit of the TMC3 register to 1. Then set the TMCE2 bit of the TMC2 register to 1 to start
<3> When the values of the TM23 register and the CR23 register connected in cascade match, the TO2 timer
<4> Then, the timer F/F is inverted during the same interval and a square wave is output from the TO2 pin.
Square-wave output operation (16-bit resolution)
• TCL2 register:
• CR2 register:
• CR3 register:
• TMC2, TCM3 registers: Stops count operation, selects the mode in which clear & start occurs on a
the count operation.
output F/F is inverted. Moreover, INTTM2 is generated and the TM23 register is cleared to 0000H.
LVS2
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
1
0
Frequency = 1/2t (N + 1): N = 0000H to FFFFH
TCL2 selects the count clock (t)
(The TCL3 register does not have to be set in cascade connection)
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
match between the TM23 register and CR23 register.
Enables timer output F/F inversion, and enables timer output.
TMC2 register = 00001011B or 00000111B
TMC3 register = 00010000B
LVR2
0
1
User’s Manual U15905EJ2V1UD
High-level output
Low-level output
Timer Output F/F Status Settings
257