UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 303

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2 Configuration
status register n (ASISn), and asynchronous serial interface transmission status register n (ASIFn). Receive data is
maintained in receive buffer register n (RXBn), and transmit data is written to transmit buffer register n (TXBn).
UARTn is controlled by asynchronous serial interface mode register n (ASIMn), asynchronous serial interface
Figure 13-3 shows the configuration of asynchronous serial interface n (UARTn).
(1) Asynchronous serial interface mode register n (ASIMn)
(2) Asynchronous serial interface status register n (ASISn)
(3) Asynchronous serial interface transmission status register n (ASIFn)
(4) Reception control parity check
(5) Receive shift register
(6) Receive buffer register n (RXBn)
(7) Transmit shift register
The ASIMn register is an 8-bit register for specifying the operation of the asynchronous serial interface.
The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs.
The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASISn
register is read.
The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed.
This register consists of a transmit buffer data flag, which indicates the hold status of TXBn data, and the
transmit shift register data flag, which indicates whether transmission is in progress.
The receive operation is controlled according to the contents set in the ASIMn register. A check for parity
errors is also performed during a receive operation, and if an error is detected, a value corresponding to the
error contents is set in the ASISn register.
This is a shift register that converts the serial data that was input to the RXDn pin into parallel data. One byte
of data is received, and if a stop bit is detected, the receive data is transferred to receive buffer register n
(RXBn).
This register cannot be directly manipulated.
RXBn is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the
MSB.
During a reception enabled state, receive data is transferred from the receive shift register to RXBn,
synchronized with the end of the shift-in processing of one frame.
Also, the reception completion interrupt request (INTSRn) is generated by the transfer of data to RXBn.
This is a shift register that converts the parallel data that was transferred from transmit buffer register n (TXBn)
into serial data.
When one byte of data is transferred from TXBn, the shift register data is output from the TXDn pin.
This register cannot be directly manipulated.
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
User’s Manual U15905EJ2V1UD
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