UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 281

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.2 Configuration
The A/D converter consists of the following hardware.
(1) Successive approximation register (SAR)
(2) A/D conversion result register (ADCR), A/D conversion result register (ADCRH)
(3) Power fail comparison threshold register (PFT)
(4) Sample & hold circuit
This register compares the voltage value of the analog input signal with the voltage tap (compare voltage)
value from the series resistor string, and holds the comparison result starting from the most significant bit
(MSB).
When the comparison result has been saved down to the least significant bit (LSB) (A/D conversion
completion), the contents of the SAR are transferred to the A/D conversion result register.
Each time A/D conversion has been completed, the result of the conversion is loaded to this register from the
successive approximation register, and the higher 10 bits of this register hold the result of the A/D conversion
(the lower 6 bits are fixed to 0).
The ADCR register is read-only, in 16-bit units. ADCR is undefined after reset.
When using only the higher 8 bits of the A/D conversion result, the ADCRH register is read-only, in 8-bit units.
Caution When data is written to the A/D converter mode register (ADM) or analog input channel
This register sets the threshold when comparing with the A/D conversion result register.
The 8-bit data set in the PFT register and the higher 8 bits (ADCRH) of the A/D conversion result register are
compared.
The PFT register can be read or written in 8-bit units.
This register is cleared to 00H after reset.
The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit and
sends the sampled data to the voltage comparator. This circuit holds the sampled analog input voltage during
A/D conversion.
Analog input
Registers
Control registers
specification register (ADS), the contents of the ADCR register may become undefined. Read
the conversion result after completion of conversion and before writing data to the ADM and
ADS registers. Otherwise, the correct conversion result may not be read.
Item
Table 11-1. Configuration of A/D Converter
12 channels (ANI0 to ANI11): V850ES/SA2
16 channels (ANI0 to ANI15): V850ES/SA3
Successive approximation register (SAR)
A/D conversion result register (ADCR)
A/D conversion result register H (ADCRH): Only higher 8 bits can be read
Power fail comparison threshold register (PFT)
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Power fail comparison mode register (PFM)
CHAPTER 11 A/D CONVERTER
User’s Manual U15905EJ2V1UD
Configuration
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