UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 219

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4
(1) Timer mode control registers 00 and 10 (TMC00 and TMC10)
Control Registers
The TMCn0 registers control the operation of TMn (n = 0, 1).
These registers can be read or written in 8-bit or 1-bit units.
Be sure to set bits 3 and 2 to 0. If they are set to 1, the operation is not guaranteed.
These registers are cleared to 00H after reset.
Cautions 1. The TMCAEn bit cannot be set at the same time as the other bits. The other bits and the
(n = 0, 1)
TMCn0
2. When conflict occurs between an overflow and a TMCn0 register write, the OVFn bit value
After reset:
registers of the other TMn units should always be set after the TMCAEn bit has been set.
Also, to use external pins related to the timer function when the 16-bit timer/event counter
is used, be sure to set (1) the TMCAEn bit after setting the external pins to control mode.
becomes the value written during the TMCn0 register write (n = 0, 1).
When TMn has counted up from FFFFH to 0000H, the OVFn bit becomes 1 and an
overflow interrupt request (INTOVFn) is generated at the same time. However, if
TMn is cleared to 0000H after a match at FFFFH when the CCn0 register is set to
compare mode (CMSn0 bit of TMCn1 register = 1) and clearing is enabled for a
match when TMn and CCn0 are compared (CCLRn bit of TMCn1 register = 1), then
TMn is considered to be cleared and the OVFn bit does not become 1. Also, no
INTOVFn interrupt is generated.
The OVFn bit retains the value 1 until 0 is written directly or until an asynchronous
reset is performed because the TMCAEn bit is 0. An interrupt operation due to an
overflow is independent of the OVFn bit, and the interrupt request flag (OVFIFn) for
INTOVFn is not affected even if the OVFn bit is manipulated. If an overflow occurs
while the OVFn bit is being read, the flag value changes, and the change is reflected
when the next read operation occurs.
OVFn
OVFn
00H
<7>
0
1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
No overflow occurs
Overflow occurs
R/W
CSn2
6
Address:
User’s Manual U15905EJ2V1UD
CSn1
5
TMC00 FFFFF606H
TMn register overflow detection
CSn0
4
3
0
TMC10 FFFFF616H
2
0
TMCEn
<1>
TMCAEn
<0>
(1/2)
217