UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 244

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3
242
Remark
(1) Timer clock selection registers 2 to 5 (TCL2 to TCL5)
The following two registers are used to control 8-bit timer/event counter n.
• Timer clock selection register n (TCLn)
• 8-bit timer mode control register n (TMCn)
Cautions 1. Before overwriting the TCLn register with different data, stop the timer operation.
Remark
Control Registers
These registers set the count clock of 8-bit timer/event counter n and the valid edge of the TIn pin input.
The TCLn register can be read or written in 8-bit units.
These registers are cleared to 00H after reset.
(a) Timer clock selection registers 2 and 3 (TCL2 and TCL3)
To use the functions of the TIn and TOn pins, refer to Table 4-18 Using Alternate Function of Port
Pins.
2. TI2 and TI3 are used alternately as P01/INTP0 and P02/INTP2, respectively, so when using
When TCL2 and TCL3 are connected in cascade, the TCL3 register settings are invalid.
(n = 2, 3)
the TIn pin function, set the PMC01 or PMC02 bit of the PMC0 register to 1 before starting
timer operation. Edge detection may not be correctly performed if the bit is manipulated
after the timer starts operating.
After reset: 00H
TCLn
TCLn2
0
7
0
0
0
0
1
1
1
1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
R/W
TCLn1
0
6
0
0
1
1
0
0
1
1
Address: TCL2 FFFFF644H, TCL3 FFFFF645H
TCLn0
User’s Manual U15905EJ2V1UD
0
1
0
1
0
1
0
1
0
5
Falling edge of TIn
Rising edge of TIn
f
f
f
f
f
f
XX
XX
XX
XX
XX
XX
/4
/8
/16
/32
/128
/512
0
4
Clock
Count clock selection
0
3
200 ns
400 ns
800 ns
1.6
6.4
25.6
TCLn2
20 MHz
µ
µ
2
µ
s
s
−
−
s
TCLn1
f
XX
1
400 ns
800 ns
1.6
3.2
12.8
51.2
10 MHz
µ
µ
µ
µ
s
s
−
−
s
s
TCLn0
0