UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 258

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4.6
connection.
mode control registers 3 and 5 (TMC3 and TMC5) to 1.
using 16-bit timer counters 23 and 45 (TM23 and TM45).
TM5.
256
The V850ES/SA2 and V850ES/SA3 are provided with a 16-bit register that can be used only during cascade
The 16-bit resolution timer/event counter mode is selected by setting the TMC34 and TMC54 bits of 8-bit timer
The external event counter counts the number of clock pulses input to the TI2 and TI4 pins from an external source
In the following description, TM2 and TM3 are used. Read TM2 and TM3 as TM4 and TM5 when using TM4 and
Setting method (when TM2 and TM3 are connected in cascade)
<1> Set each register.
<2> Set the TMCE3 bit of the TMC3 register to 1. Then set the TMCE2 bit of the TMC2 register to 1 and
<3> When the values of the TM23 register and CR23 register connected in cascade match, INTTM2 is
<4> INTTM2 is then generated each time the values of the TM23 register and CR23 register match.
Operation as external event counter (16 bits)
• TCL2 register:
• CR2 register:
• CR3 register:
• TMC2, TMC3 registers: Stops count operation, selects the clear & stop mode entered on a match
count the number of pulses input from TI2.
generated (the TM23 register is cleared to 0000H).
Cautions 1. During external event counter operation, do not rewrite the value of the CRn register.
INTTM2 is generated when the valid edge of TI2 is input N + 1 times: N = 0000 to FFFFH
2. To write using 8-bit access during cascade connection, set the TMCE3 bit to 1 and
3. During cascade connection, TI2 input and INTTM2 input are used while TI3 input, TO3
4. Do not change the value of the CR23 register during external counter operation.
then set the TMCE2 bit to 1. When operation is stopped, set the TMCE2 bit to 0 and
then set the TMCE3 bit to 0.
output, and INTTM3 input are not, so set bits LVS3, LVR3, TMC31, and TOE3 to 0.
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
Selects the TI2 input edge.
(The TCL3 register does not have to be set during cascade connection.)
Falling edge of TI2 → TCL2 = 00H
Rising edge of TI2 → TCL2 = 01H
Compare value (N) ... Lower 8 bits (settable from 00H to FFH)
Compare value (N) ... Higher 8 bits (settable from 00H to FFH)
between the TM23 register and CR23 register, disables timer output F/F
inversion, and disables timer output.
(×: don’t care)
TMC2 register = 0000xx00B
TMC3 register = 0001xx00B
User’s Manual U15905EJ2V1UD