UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 308

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

306
(2) Asynchronous serial interface status register n (ASISn)
The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when
UARTn reception is complete.
The status flag, which indicates a reception error, always indicates the status of the error that occurred most
recently. That is, if the same error occurred several times before the receive data was read, this flag would
hold only the status of the error that occurred last.
The ASISn register is cleared to 00H by a read operation. When a reception error occurs, receive buffer
register n (RXBn) should be read and the error flag should be cleared after the ASISn register is read.
This register is read-only, in 8-bit units.
This register is cleared to 00H after reset.
Caution When the UARTCAEn bit or RXEn bit of the ASIMn register is set to 0, or when the ASISn
(n = 0, 1)
register is read, the PEn, FEn, and OVEn bits of the ASISn register are cleared (0).
After reset:
ASISn
• The operation of the PEn bit differs according to the settings of the PS1 and PS0
• For receive data stop bits, only the first bit is checked regardless of the stop bit
• When an overrun error occurs, the next receive data value is not written to the
OVEn
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
PEn
FEn
bits of the ASIMn register.
length.
RXBn register and the data is discarded.
00H
0
1
0
1
0
1
7
0
When the ASIMn register’s UARTCAEn and RXEn bits are both set to 0,
or when the ASISn register has been read
When reception was completed, the transmit data parity did not match
the parity bit
When the ASIMn register’s UARTCAEn and RXEn bits are both set to 0,
or when the ASISn register has been read
When reception was completed, no stop bit was detected
When the ASIMn register’s UARTCAEn and RXEn bits are both 0, or
when the ASISn register has been read.
UARTn completed the next receive operation before reading the RXBn
receive data.
R
6
0
Address: ASIS0
User’s Manual U15905EJ2V1UD
5
0
Status flag that indicates an overrun error
Status flag that indicates a framing error
Status flag that indicates a parity error
FFFFFA03H, ASIS1 FFFFFA13H
4
0
3
0
PEn
2
FEn
1
OVEn
0