UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 453

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6 Exception Trap
V850ES/SA2 and V850ES/SA3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an
exception trap.
17.6.1 Illegal opcode definition
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
The following illustrates the processing of the exception trap.
control.
that it not be used.
×: Arbitrary
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
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User’s Manual U15905EJ2V1UD
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