UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 357

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note This flag’s signal is invalid when IICE = 0.
Condition for clearing (WREL = 0)
• Automatically cleared after execution
• After reset
Condition for clearing (SPIE = 0)
• Cleared by instruction
• After reset
This bitÕs setting is invalid during an address transfer and is valid as the transfer is completed. When in
master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave
device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ACK
signal is issued. When the slave device has received an extension code, a wait is inserted at the falling
edge of the eighth clock.
Condition for clearing (WTIM = 0)
• Cleared by instruction
• After reset
WREL
WTIM
SPIE
0
1
0
1
0
1
Wait not canceled
Wait canceled. This setting is automatically cleared after wait is canceled.
Disabled
Enabled
Interrupt request is generated at the eighth clockÕs falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master
Interrupt request is generated at the eighth clockÕs falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master
Enable/disable generation of interrupt request when stop condition is detected
device.
device.
Note
Note
Note
Control of wait and interrupt request generation
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Wait cancellation control
Condition for setting (WREL = 1)
• Set by instruction
Condition for setting (SPIE = 1)
• Set by instruction
Condition for setting (WTIM = 1)
• Set by instruction
2
C BUS
(2/4)
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