UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 425

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(8) DMA transfer in progress can be stopped by clearing the Enn bit of the DCHCn register to 0 during DMA
(9) The INIT bit is used to initialize DMA; however, if the setting of the INIT bit and the DMA transfer of another
transfer.
Follow either of the procedures below to clear the Enn bit of the DCHCn register to 0.
(a) To discard all transfers in progress and start DMA transfer from the beginning
(b) To interrupt and resume the transfer in progress
channel conflict, initialization processing is not performed. Set the INIT bit following either of the procedures
below.
(a) To temporarily stop the transfers of all DMA channels
<1> Stop generation of the DMA transfer start factor (stop the DMA operation).
<2> Make sure that the DFn bit of the DTFRn register is cleared to 0 (clear the bit if set).
<3> After making sure that the DFn bit of the DTFRn register is cleared to 0, clear the Enn bit of the
<4> Set the INITn bit of the DCHCn register (this operation initializes the transfer status).
<1> Stop generation of the DMA transfer start factor (stop the DMA operation).
<2> Make sure that the DFn bit of the DTFRn register is cleared to 0 (if set, wait until the pending DMA
<3> After making sure that the DFn bit of the DTFRn register is cleared to 0, clear the Enn bit of the
<4> Set the Enn bit of the DCHCn register to 1 to resume DMA transfer.
<5> Start the operation of the DMA transfer start factor that was stopped.
<1> Disable interrupts (DI).
<2> Read the Enn bits of the DCHCn registers of the DMA channels in use other than the channel to be
<3> Clear the Enn bits of the DMA channels in use (including the channel to be initialized) to 0. For the
<4> Set the INITn bit of the channel to be initialized to 1.
<5> Read the TCn bit of each of the channels not to be forcibly stopped. If the TCn and Enn bits of each
<6> Write the values of the Enn bits manipulated in step <5> above to the DCHCn register.
<7> Enable interrupts (EI).
DCHCn register to 0.
transfer requests have been completed).
DCHCn register to 0 (this operation interrupts DMA transfer).
initialized and transfer the read value to a general-purpose register.
last DMA channel, execute the clear instruction for the Enn bit twice
For example, execute the following instructions when channels 0, 1, and 2 are used.
• Clear E00 of the DCHC0 register to 0
• Clear E11 of the DCHC1 register to 0
• Clear E22 of the DCHC2 register to 0
• Clear E22 of the DCHC2 register to 0
channel not to be initialized, and the read TCn bit and the value read in <2> are 1 (the ANDed values
are 1), clear the saved Enn bit to 0.
Note If the transfer target (transfer source or transfer destination) is the internal RAM, execute the
Caution 1. Always perform step <5> to prevent the Enn bit of the channels successfully
instruction three times.
completed in <2> and <3> from being illegally set.
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U15905EJ2V1UD
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