SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 159

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.20.7.4
10.20.7.5
10.20.7.6
• Priority, byte offset 3
• Priority, byte offset 2
• Priority, byte offset 1
• Priority, byte offset 0
Each priority field holds a priority value, 0-15. The lower the value, the greater the priority of the corresponding interrupt.
The processor implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
See
interrupt priority array, that provides the software view of the interrupt priorities.
6500C–ATARM–8-Feb-11
“The CMSIS mapping of the Cortex-M3 NVIC registers” on page 151
31
23
15
31
23
15
31
23
15
7
7
7
IPR2
IPR1
IPR0
30
22
14
30
22
14
30
22
14
6
6
6
29
21
13
29
21
13
29
21
13
5
5
5
28
20
12
28
20
12
28
20
12
4
4
4
Reserved
IP[11]
IP[10]
IP[9]
IP[8]
IP[6]
IP[5]
IP[4]
IP[3]
IP[2]
IP[1]
IP[0]
27
19
11
27
19
11
27
19
11
3
3
3
for more information about the IP[0] to IP[34]
26
18
10
26
18
10
26
18
10
2
2
2
25
17
25
17
25
17
9
1
9
1
9
1
SAM3S
24
16
24
16
24
16
8
0
8
0
8
0
159

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