SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 618

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31.6.2
31.6.3
31.7
31.7.1
Figure 31-3.
Figure 31-4. Transfer Format
31.7.2
618
Functional Description
SAM3S
Power Management
Interrupt
Transfer Format
Modes of Operation
START and STOP Conditions
TWD
TWCK
The TWI interface may be clocked through the Power Management Controller (PMC), thus the
programmer must first configure the PMC to enable the TWI clock.
The TWI interface has an interrupt line connected to the Nested Vector Interrupt Controller
(NVIC). In order to handle interrupts, the NVIC must be programmed before configuring the TWI.
Table 31-5.
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see
31-4).
Each transfer begins with a START condition and terminates with a STOP condition (see
31-3).
The TWI has six modes of operations:
• Enable the peripheral clock.
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
• Master transmitter mode
• Master receiver mode
Start
Instance
TWI0
TWI1
Address
TWCK
TWD
Peripheral IDs
R/W
Start
Ack
19
20
ID
Data
Ack
Data
Stop
Ack
Stop
6500C–ATARM–8-Feb-11
Figure
Figure