SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 208

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.23.8.3
10.23.8.4
10.23.9
208
SAM3S
MPU design hints and tips
Subregions
Example of SRD use
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the correspond-
ing bit in the SRD field of the RASR to disable a subregion, see
Register” on page
significant bit controls the last subregion. Disabling a subregion means another region overlap-
ping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions, With regions of these sizes, you
must set the SRD field to 0x00, otherwise the MPU behavior is Unpredictable.
Two regions with the same base address overlap. Region one is 128KB, and region two is
512KB. To ensure the attributes from region one apply to the first128KB region, set the SRD
field for region two to b00000011 to disable the first two subregions, as
Figure 10-9. SRD use
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region
that the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused
regions to prevent any previous region settings from affecting the new MPU setup.
• except for the RASR, it must use aligned word accesses
• for the RASR it can use byte or aligned halfword or word accesses.
Base address of both regions
203. The least significant bit of SRD controls the first subregion, and the most
; and Region Attribute, Size and Enable
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
“MPU Region Attribute and Size
Figure 10-9
512KB
448KB
384KB
320KB
256KB
192KB
128KB
Offset from
base address
64KB
0
6500C–ATARM–8-Feb-11
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