SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 869

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.6.4
6500C–ATARM–8-Feb-11
PWM Event Lines
The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in
particular for ADC (Analog-to-Digital Converter)).
A pulse (one cycle of the master clock (MCK)) is generated on an event line, when at least one
of the selected comparisons is matching. The comparisons can be selected or unselected inde-
pendently by the CSEL bits in the
Line x).
Figure 36-16. Event Line Block Diagram
CMPS0 (PWM_ISR2)
CSEL0 (PWM_ELxMR)
CMPS1 (PWM_ISR2)
CSEL1 (PWM_ELxMR)
CMPS2 (PWM_ISR2)
CSEL2 (PWM_ELxMR)
CMPS7 (PWM_ISR2)
CSEL7 (PWM_ELxMR)
“PWM Event Line x Register”
GENERATOR
PULSE
(PWM_ELxMR for the Event
Event Line x
SAM3S
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