SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 366
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SAM3S4B
Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.7
23.7.1
23.7.1.1
23.7.1.2
23.7.1.3
366
Application Example
SAM3S
Implementation Examples
8-bit NAND Flash
Hardware Configuration
Software Configuration
Hardware configurations are given for illustration only. The user should refer to the manufacturer
web site to check for memory device availability.
For Hardware implementation examples, please refer to ATSAM3S-EK schematics, which show
examples of a connection to an LCD module and NAND Flash.
Perform the following configuration:
In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE
don’t care”, connect NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
• Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS Register
• Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled
• NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND
(ANY PIO)
NANDOE
NANDWE
(ANY PIO)
on the Bus Matrix User Interface.
respectively by setting to 1 the address bits A21 and A22 during accesses.
must be programmed in peripheral mode in the PIO controller.
Flash timings, the data bus width and the system bus frequency.
D[0..7]
CLE
ALE
3V3
R1
R1
R2
R2
10K
10K
10K
10K
16
17
18
19
10
11
14
15
20
21
22
23
24
25
26
8
9
7
1
2
3
4
5
6
U1
U1
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
TSOP48 PACKAGE
2 Gb
K9F2G08U0M
K9F2G08U0M
PRE
VCC
VCC
VSS
VSS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
D0
D1
D2
D3
D4
D5
D6
D7
C1
C1
100NF
100NF
3V3
C2
C2
100NF
100NF
6500C–ATARM–8-Feb-11
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