SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 385
SAM3S4B
Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 23-22. TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
23.12 External Wait
23.12.1
6500C–ATARM–8-Feb-11
write2 controlling signal
read1 controlling signal
Restriction
A[23:0]
(NWE)
(NRD)
D[7:0]
MCK
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be
set to either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00”
(disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT
signal delays the read or write operation in regards to the read or write controlling signal,
depending on the read and write modes of the corresponding chip select.
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode
(“Slow Clock Mode” on page
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
TDF_CYCLES = 5
read1 cycle
read1 hold = 1
(“Asynchronous Page Mode” on page
Read to Write
Wait State
391).
TDF_CYCLES = 5
4 TDF WAIT STATES
393), or in Slow Clock Mode
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
SAM3S
385
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