SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 39

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SAM3S4B

Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3S4B

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10. ARM Cortex
10.1
10.2
10.3
6500C–ATARM–8-Feb-11
About this section
Embedded Characteristics
About the Cortex-M3 processor and core peripherals
®
M3 Processor
This section provides the information required for application and system-level software devel-
opment. It does not provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have
no experience of ARM products.
Note: The information in this section is reproduced from source material provided to Atmel by
ARM Ltd. in terms of Atmel’s license for the ARM Cortex
is copyright ARM Ltd., 2008 - 2009.
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Single cycle 32-bit multiply
• Hardware divide
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
• SysTick Timer
• Nested Vectored Interrupt Controller
• The Cortex-M3 processor is a high performance 32-bit processor designed for the
• outstanding processing performance combined with fast interrupt handling
microcontroller market. It offers significant benefits to developers, including:
– 24-bit down counter
– Self-reload capability
– Flexible System timer
– Thirty maskable external interrupts
– Sixteen priority levels
– Processor state automatically saved on interrupt entry, and restored on
– Dynamic reprioritization of interrupts
– Priority grouping
– Support for tail-chaining and late arrival of interrupts
– Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead.
selection of preempting interrupt levels and non-preempting interrupt levels.
back-to-back interrupt processing without the overhead of state saving and
restoration between interrupts.
-M3 processor core. This information
SAM3S
39

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