SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 377
SAM3S4B
Manufacturer Part Number
SAM3S4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3S4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
64 MHz
Cpu
Cortex-M3
# Of Touch Channels
23
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
48
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.10 Automatic Wait States
23.10.1
Figure 23-13. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
23.10.2
6500C–ATARM–8-Feb-11
Chip Select Wait States
Early Read Wait State
A[23:0]
D[7:0]
NCS0
NCS2
NWE
MCK
NRD
When multiple chip selects are handled, it is possible to configure the scrambling function per
chip select using the OCMS field in the SMC_OCMS registers.
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle
cycle ensures that there is no bus contention between the de-activation of one device and the
activation of the next one.
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are
all set to 1.
Figure 23-13
Select 2.
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
illustrates a chip select wait state between access on Chip Select 0 and Chip
NRD_CYCLE
Read to Write
Wait State
Chip Select
Wait State
NWE_CYCLE
SAM3S
377
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