SAM3S4B Atmel Corporation, SAM3S4B Datasheet - Page 351

• Manufacturer Part Number: SAM3S4B
• Manufacturer: Atmel Corporation

Specifications of SAM3S4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 64 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 23
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1000
• Analog Comparators: 1
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 48
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

22.6
22.7
6500C–ATARM–8-Feb-11
System I/O Configuration
Write Protect Registers
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in
System I/O mode (such as JTAG, ERASE, USB, etc...) or as general purpose I/O lines. Enabling
or disabling the corresponding I/O lines in peripheral mode or in PIO mode (PIO_PER or
PIO_PDR registers) in the PIO controller as no effect. However, the direction (input or output),
pull-up, pull-down and other mode control is still managed by the PIO controller.
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX
address space from address offset 0x000 to 0x1FC can be write-protected by setting the
WPEN bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC
is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR)
is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR)
with the appropriate access key WPKEY.
SAM3S
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