mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 104

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Power Management
loop:
4.6 Power Management
Because processor memory references may be simultaneously sent to an SRAM module
and cache, power can be minimized by configuring RAMBAR address space masks as
precisely as possible. For example, if an SRAM is mapped to the internal instruction bus
and contains instruction data, setting the ASn mask bits associated with operand references
can decrease power dissipation. Similarly, if the SRAM contains data, setting ASn bits
associated with instruction fetches minimizes power.
Table 4-2 shows typical RAMBAR configurations.
4.7 Cache Overview
This section describes the MCF5307 cache implementation, including organization,
configuration, and coherency. It describes cache operations and how the cache interacts
with other memory structures.
The MCF5307 processor contains a nonblocking, 8-Kbyte, 4-way set-associative, unified
(instruction and data) cache with a 16-byte line size. The cache improves system
performance by providing low-latency access to the instruction and data pipelines. This
decouples processor performance from system memory performance, increasing bus
availability for on-chip DMA or external devices. Figure 4-2 shows the organization and
integration of the data cache.
4-6
.
move.l
asr.l
.align
movem.l
movem.l
lea.l
lea.l
subq.l
bne.b
movem.l
lea.l
rts
Table 4-2. Examples of Typical RAMBAR Settings
Code only
Data only
Both code and data
Data Contained in SRAM
24(a7),d4
#4,d4
4
(a0),#0xf
#0xf,(a1)
16(a0),a0
16(a1),a1
#1,d4
loop
(a7),#0x1c
12(a7),a7
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MCF5307 User’s Manual
;load byte count
;divide by 16 to convert to loop count
;force loop on 0-mod-4 address
;read 16 bytes from source
;store into RAM destination
;increment source pointer
;increment destination pointer
;decrement loop counter
;if done, then exit, else continue
;restore d2/d3/d4 registers
;deallocate temporary space
RAMBAR[5–0]
0x2B
0x35
0x21