mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 268

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Example
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next
access to the SDRAM address space generates the
address of the access should be selected to place the correct mode information on the
SDRAM address pins. The address is not multiplexed for the
access can be a read or write. The important thing is that the address output of that access
needs the correct mode programming information on the correct address bits.
Figure 11-24 shows the
11.5 SDRAM Example
This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5307
operating at 40 MHz. Table 11-32 lists design specifications for this example.
11-34
Speed grade (-8E)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV
Period between auto refresh and
ACTV
Precharge command to
Last data input to
Auto refresh period for 4096 rows (t
-to-read/write delay (t
command to precharge command (t
Figure 11-24. Mode Register Set (
Table 11-32. SDRAM Example Specifications
SRAS, SCAS
Freescale Semiconductor, Inc.
RAS[1] or [0]
MRS
PALL
For More Information On This Product,
DRAMW
BCLKO
A[31:0]
D[31:0]
command, which occurs in the first clock of the bus cycle.
command (t
Parameter
ACTV
RCD
Go to: www.freescale.com
command (t
)
MCF5307 User’s Manual
ACTV
RWL
REF
MRS
command (t
)
)
RAS
RP
)
)
RC
)
MRS
MRS
command to that SDRAM. The
40 MHz (25-nS period)
20 nS (min.)
70 nS
48 nS (min.)
20 nS (min.)
1 bus clock (25 nS)
64 mS
) Command
Specification
MRS
command. The
MRS