mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 199
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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7.2.4 PLL Control Register (PLLCR)
The PLL control register (PLLCR), Figure 7-2, provides control over the PLL.
Table 7-1 describes PLLCR bits.
7.3 PLL Port List
Table 7-2 describes PLL module inputs.
CLKIN
RSTI
6–4
3–0
Bit
7
SIgnal
Address
Reset
Field ENBSTOP
ENBSTOP
R/W
PLLIPL
Name
—
Input clock to the PLL. Input frequency must not be changed during operation. Changes are
recognized only at reset.
Active-low asynchronous input that, when asserted, indicates PLL is to enter reset mode. As long as
RSTI is asserted, the PLL is held in reset and does not begin to lock.
7
Enable CPU STOP instruction. Must be set for the ColdFire CPU STOP instruction to be
acknowledged. Cleared at reset and must be subsequently set for the processor to enter
low-power modes. Only clocks to the core are turned off because of the CPU STOP instruction.
Internal modules remain clocked and can generate interrupts to restart the ColdFire core.
0 Disable CPU STOP
1 Enable CPU STOP; STOP instruction turns off clocks to the ColdFire core.
PLL interrupt priority level to wake up from CPU STOP. Determines the minimum level an
interrupt (decoded as an interrupt priority level) must be to waken the PLL. The PLL then turns
clocks back on to the core processor and interrupt exception processing occurs.
000 Any interrupts can wake core
001 Interrupts 2–7
010 Interrupts 3–7
011 Interrupts 4–7
100 Interrupts 5–7
101 Interrupts 6–7
110 Interrupt 7 only
111 No interrupts can wake core. Any reset, including a watchdog reset, can wake the core.
No PLL phase lock time is required.
Reserved, should be cleared.
Figure 7-2. PLL Control Register (PLLCR)
Freescale Semiconductor, Inc.
6
Table 7-1. PLLCR Field Descriptions
Table 7-2. PLL Module Input SIgnals
For More Information On This Product,
Chapter 7. Phase-Locked Loop (PLL)
PLLIPL
Go to: www.freescale.com
5
MBAR + 0x08
4
0000_0000
Description
R/W
Description
3
2
—
1
PLL Port List
0
7-3
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