mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 119

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

4.10 Cache Registers
This section describes the MCF5307 implementation of the Version 3 cache registers.
4.10.1 Cache Control Register (CACR)
The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the
MOVEC register instruction and can be read or written from the debug facility. A hardware
reset clears CACR, which disables the cache; however, reset does not affect the tags, state
information, or data in the cache.
Table 4-4 describes CACR fields.
31
30
29
28
Bits
Reset
Reset
Field EC
Field
R/W
R/W
Rc
—
ESB
Name
31
15
DPI
EC
—
30
14
Enable cache.
0 Cache disabled. The cache is not operational, but data and tags are preserved.
1 Cache enabled.
Reserved, should be cleared.
Enable store buffer.
0 Writes to write-through or noncachable in imprecise mode bypass the store buffer and
1 The four-entry FIFO store buffer is enabled; when imprecise mode is used, this buffer defers
Cache-inhibited, precise-mode accesses always bypass the store buffer.
Disable CPUSHL invalidation.
0 Normal operation. A CPUSHL instruction causes the selected line to be pushed if modified and
1 No clear operation. A CPUSHL instruction causes the selected line to be pushed if modified,
ESB
generate bus cycles directly. Section 4.9.5.2.1, “Push and Store Buffers,” describes the
performance penalty for this.
pending writes to write-through or cache-inhibited regions to maximize performance.
then invalidated.
then left valid.
29
13
—
Figure 4-8. Cache Control Register (CACR)
DPI
28
12
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-4. CACR Field Descriptions
HLCK
27
11
Chapter 4. Local Memory
Go to: www.freescale.com
DNFB
26
10
Write (R/W by debug module)
Write (R/W by debug module)
—
0000_0000_0000_0000
0000_0000_0000_0000
25
9
DCM
CINVA
0x002
24
8
Description
23
7
—
DW
20
—
19
Cache Registers
—
18
17
4-21
16
0