mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 272

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Example
11.5.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register
setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the
corresponding MCF5307 address pins must be determined while being aware of masking
requirements.
Table 11-37 lists the desired initialization setting:
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how
DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before
the mode register bit is set, DMR0[19] must be set to enable masking.
11-38
Setting
Setting
(hex)
(hex)
Field
Field
31
15
X
0
Figure 11-29. Mode Register Mapping to MCF5307 A[31:0]
30
14
X
0
MCF5307 Pins
0
0
29
13
X
0
A20
A19
A18
A17
A10
A11
A12
A13
A14
A15
A9
Table 11-37. Mode Register Initialization
Freescale Semiconductor, Inc.
28
12
X
0
For More Information On This Product,
27
11
X
1
SDRAM Pins
Go to: www.freescale.com
MCF5307 User’s Manual
26
10
X
0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
8
25
X
0
9
24
X
X
8
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
23
WB
X
X
BT
7
BL
BL
BL
22
X
X
6
0
0
21
X
X
5
20
X
X
4
X
0
0
0
0
0
1
0
0
0
0
19
X
0
3
18
X
0
2
0
0
17
X
0
1
16
X
V
X
0