mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 421

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions (Continued)
1
The bus arbitration state diagram can be used for the MCF5307 three-wire bus arbitration
protocol to approximate the high-level behavior of the MCF5307. It is assumed that all TS
or AS signals in a system are tied together and each bus device’s BD and BR signals are
connected individually to the external arbiter. The external arbiter must ensure that any
external masters will have released the bus after the next rising edge of before asserting BG
to the MCF5307. The MCF5307 does not monitor external bus master operation regarding
bus arbitration.
18.10 Reset Operation
The MCF5307 supports two types of reset. Asserting RSTI resets the entire MCF5307. A
software watchdog reset resets everything but the internal PLL module.
External
Current
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
Explicit
master
master
State
Condition
Label
C1
C2
C3
C4
C5
D1
D2
D3
D4
The MCF5307 can start a transfer on the rising edge of the
cycle after BG is asserted. The external arbiter should not assert
BG to the MCF5307 until the previous external master stops
driving the bus or the part may be damaged.
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
RSTI
Freescale Semiconductor, Inc.
For More Information On This Product,
Watchdog
Software
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Chapter 18. Bus Operation
Reset
Go to: www.freescale.com
NOTE:
Negated
Asserted
Asserted
Asserted
Asserted
Negated
Negated
Negated
Negated
BG
1
Asserted
Request
Negated
Bus
—
—
—
—
—
—
—
Progress
Transfer
Negated
Yes
Yes
—
—
—
—
—
—
in
Negated
Cycle
End of
Yes
—
—
—
—
—
—
—
Reset Operation
1
Next State
External
External
External
Explicit
Explicit
Explicit
Explicit
Implicit
Explicit
master
master
master
master
master
master
master
master
master
device
device
device
18-33