mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 168

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Real-Time Debug Support
5.6.1 Theory of Operation
Breakpoint hardware can be configured to respond to triggers in several ways. The response
desired is programmed into TDR. As shown in Table 5-21, when a breakpoint is triggered,
an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not
displaying captured processor status, operands, or branch addresses.
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR
read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a
level-2 breakpoint is not enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the
system operates, a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are
initiated before the excepting instruction is executed. All other breakpoint events are
recognized on the processor’s local bus, but are made pending to the processor and sampled
like other interrupt conditions. As a result, these interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With
TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this
configuration, TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the
processor, which is treated higher than the nonmaskable level-7 interrupt request. As with
all interrupts, it is made pending until the processor reaches a sample point, which occurs
once per instruction. Again, the hardware forces the PC breakpoint to occur before the
targeted instruction executes. This is possible because the PC breakpoint is enabled when
interrupt sampling occurs. For address and data breakpoints, reporting is considered
imprecise because several instructions may execute after the triggering address or data is
detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates
exception processing. This event is signaled externally by the assertion of a unique PST
value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception
processing begins. After the standard 8-byte exception stack is created, the processor
5-40
1
Encodings not shown are reserved for future use.
Table 5-21. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
DDATA[3:0]/CSR[BSTAT]
Freescale Semiconductor, Inc.
0000/0000
0010/0001
0100/0010
1010/0101
1100/0110
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MCF5307 User’s Manual
1
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
Breakpoint Status