mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 8

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Paragraph
Number
4.9.5
4.9.5.1
4.9.5.2
4.9.5.2.1
4.9.5.2.2
4.9.6
4.10
4.10.1
4.10.2
4.11
4.12
4.12.1
4.13
5.1
5.2
5.3
5.3.1
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.5
5.5.1
5.5.2
5.5.2.1
5.5.2.2
5.5.3
5.5.3.1
5.5.3.1.1
5.5.3.2
5.5.3.3
5.5.3.3.1
5.5.3.3.2
5.5.3.3.3
viii
Cache Registers................................................................................................. 4-21
Cache Management........................................................................................... 4-24
Cache Operation Summary ............................................................................... 4-25
Cache Initialization Code.................................................................................. 4-29
Overview............................................................................................................. 5-1
Signal Description............................................................................................... 5-2
Real-Time Trace Support.................................................................................... 5-3
Programming Model ........................................................................................... 5-5
Background Debug Mode (BDM) .................................................................... 5-16
Memory Accesses for Cache Maintenance................................................... 4-17
Cache Locking .............................................................................................. 4-19
Cache Control Register (CACR) .................................................................. 4-21
Access Control Registers (ACR0–ACR1).................................................... 4-22
Cache State Transitions ................................................................................ 4-25
Begin Execution of Taken Branch (PST = 0x5) ............................................. 5-4
Address Attribute Trigger Register (AATR) .................................................. 5-7
Address Breakpoint Registers (ABLR, ABHR) ............................................ 5-8
BDM Address Attribute Register (BAAR)..................................................... 5-9
Configuration/Status Register (CSR)............................................................ 5-10
Data Breakpoint/Mask Registers (DBR, DBMR)......................................... 5-12
Program Counter Breakpoint/Mask Registers (PBR, PBMR)...................... 5-13
Trigger Definition Register (TDR) ............................................................... 5-14
CPU Halt....................................................................................................... 5-16
BDM Serial Interface.................................................................................... 5-17
BDM Command Set...................................................................................... 5-19
Cache Filling............................................................................................. 4-17
Cache Pushes ............................................................................................ 4-18
Receive Packet Format ............................................................................. 5-19
Transmit Packet Format............................................................................ 5-19
ColdFire BDM Command Format............................................................ 5-20
Command Sequence Diagrams................................................................. 5-21
Command Set Descriptions ...................................................................... 5-23
Push and Store Buffers ......................................................................... 4-18
Push and Store Buffer Bus Operation................................................... 4-18
Extension Words as Required............................................................... 5-21
Read A/D Register (
Write A/D Register (
Read Memory Location (
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MCF5307 User’s Manual
CONTENTS
Debug Support
Chapter 5
RAREG
WAREG
Title
READ
/
RDREG
/
WDREG
)............................................................ 5-26
) ..................................................... 5-24
)................................................... 5-25
Number
Page