mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 207

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

determines the relative priority of competing devices. A device loses arbitration if it sends
logic high while another sends logic low; it immediately switches to slave-receive mode
and stops driving SDA. In this case, the transition from master to slave mode does not
generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of
arbitration.
8.4.2 Clock Synchronization
Because wire-AND logic is used, a high-to-low transition on SCL affects devices
connected to the bus. Devices start counting their low period when the master drives SCL
low. When a device clock goes low, it holds SCL low until the clock high state is reached.
However, the low-to-high change in this device clock may not change the state of SCL if
another device clock is still in its low period. Therefore, the device with the longest low
period holds the synchronized clock SCL low. Devices with shorter low periods enter a high
wait state during this time (See Figure 8-4). When all devices involved have counted off
their low period, the synchronized clock SCL is released and pulled high. There is then no
difference between device clocks and the state of SCL, so all of the devices start counting
their high periods. The first device to complete its high period pulls SCL low again.
8.4.3 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfers. Slave
devices can hold SCL low after completing one byte transfer (9 bits). In such a case, the
clock mechanism halts the bus clock and forces the master clock into wait states until the
slave releases SCL.
8.4.4 Clock Stretching
Slaves can use the clock synchronization mechanism to slow down the transfer bit rate.
After the master has driven SCL low, the slave can drive SCL low for the required period
and then release it. If the slave SCL low period is longer than the master SCL low period,
the resulting SCL bus signal low period is stretched.
SCL1
SCL2
SCL
Freescale Semiconductor, Inc.
Figure 8-4. Synchronized Clock SCL
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Chapter 8. I
2
Wait
C Module
Start counting high period
I
2
C Protocol
8-5