mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 422

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Reset Operation
18.10.1 Master Reset
To perform a master reset, an external device asserts RSTI. When power is applied to the
system, external circuitry should assert RSTI for a minimum of 80 CLKIN cycles after Vcc
is within tolerance. Figure 18-33 is a functional timing diagram of the master reset
operation, showing relationships among Vcc, RSTI, mode selects, and bus signals. CLKIN
must be stable by the time Vcc reaches the minimum operating specification. CLKIN
should start oscillating as Vcc is ramped up to clear out contention internal to the MCF5307
caused by the random states of internal flip-flops on power up. RSTI is internally
synchronized for two CLKIN cycles before being used and must meet the specified setup
and hold times in relationship to CLKIN to be recognized.
During the master reset period, all signals capable of being three-stated are driven to a
high-impedance; all others are negated. When RSTI negates, all bus signals remain in a
high-impedance state until the MCF5307 is granted the bus and the core begins the first bus
cycle for reset exception processing. A master reset causes any bus cycle (including DRAM
refresh cycle) to terminate and initializes registers appropriately for a reset exception.
Note that during reset D[7:0] are sampled on the negating edge of RSTI for initial
MCF5307 configurations listed in Table 18-12.
18-34
Bus Signals
CLKIN
RSTO
D[7:0]
RSTI
VCC
BR
BD
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 18-33. Master Reset Timing
Go to: www.freescale.com
MCF5307 User’s Manual
>80 CLKIN cycles
100K CLKIN cycles
PLL lock time