mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 22

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Figure
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11-15
11-16
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11-29
12-1
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xxii
DRAM Control Register (DCR) (Synchronous Mode) ............................................ 11-19
DACR0 and DACR1 Registers (Synchronous Mode).............................................. 11-20
DRAM Controller Mask Registers (DMR0 and DMR1).......................................... 11-22
Burst Read SDRAM Access ..................................................................................... 11-28
Burst Write SDRAM Access .................................................................................... 11-29
Synchronous, Continuous Page-Mode Access—Consecutive Reads....................... 11-30
Synchronous, Continuous Page-Mode Access—Read after Write........................... 11-31
Auto-Refresh Operation............................................................................................ 11-32
Self-Refresh Operation ............................................................................................. 11-32
Mode Register Set (mrs) Command ......................................................................... 11-34
Initialization Values for DCR ................................................................................... 11-35
SDRAM Configuration............................................................................................. 11-36
DACR Register Configuration.................................................................................. 11-36
DMR0 Register ......................................................................................................... 11-37
Mode Register Mapping to MCF5307 A[31:0] ........................................................ 11-38
DMA Signal Diagram ................................................................................................. 12-1
Dual-Address Transfer................................................................................................ 12-3
Single-Address Transfers............................................................................................ 12-4
Source Address Registers (SARn) .............................................................................. 12-6
Destination Address Registers (DARn) ...................................................................... 12-7
Byte Count Registers (BCRn)—BCR24BIT = 1 ........................................................ 12-7
BCRn—BCR24BIT = 0.............................................................................................. 12-8
DMA Interrupt Vector Registers (DIVRn) ............................................................... 12-11
DREQ Timing Constraints, Dual-Address DMA Transfer....................................... 12-15
Dual-Address, Peripheral-to-SDRAM, Lower-Priority DMA Transfer ................... 12-16
Single-Address DMA Transfer ................................................................................. 12-17
Timer Block Diagram ................................................................................................. 13-1
Timer Mode Registers (TMR0/TMR1) ...................................................................... 13-3
Timer Reference Registers (TRR0/TRR1) ................................................................. 13-4
Timer Capture Register (TCR0/TCR1) ...................................................................... 13-5
Timer Counters (TCN0/TCN1)................................................................................... 13-5
Timer Event Registers (TER0/TER1)......................................................................... 13-5
Simplified Block Diagram .......................................................................................... 14-1
UART Mode Registers 1 (UMR1n)............................................................................ 14-5
UART Mode Register 2 (UMR2n) ............................................................................. 14-6
UART Status Register (USRn) ................................................................................... 14-7
UART Clock-Select Register (UCSRn)...................................................................... 14-8
UART Command Register (UCRn)............................................................................ 14-9
UART Receiver Buffer (URB0) ............................................................................... 14-11
UART Transmitter Buffer (UTB0)........................................................................... 14-12
UART Input Port Change Register (UIPCRn).......................................................... 14-12
DMA Control Registers (DCRn) ............................................................................... 12-8
DMA Status Registers (DSRn) ................................................................................ 12-10
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MCF5307 User’s Manual
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