mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 414

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

General Operation of External Master Transfers
shown in Figure 18-25, the MCF5307 continues to assert BD until the completion of the
bus cycle. If BG is negated by the end of the bus cycle, the MCF5307 negates BD. While
BG is asserted, BD remains asserted to indicate the MCF5307 is master, and it continuously
drives the address bus, attributes, and control signals.
In the second situation, the bus is granted to the MCF5307, but it does not have an internal
bus request pending, so it takes implicit bus mastership. The MCF5307 does not drive the
bus and does not assert BD if the bus has an implicit master. If an internal bus request is
generated, the MCF5307 assumes explicit bus mastership. If explicit mastership was
assumed because an internal request was generated, the MCF5307 immediately begins an
access and asserts BD.
In Figure 18-28, the external device is bus master during C1 and C2. During C3 the external
device releases control of the bus by asserting BG to the MCF5307. At this point, there is
an internal access pending so the MCF5307 asserts BD during C4 and begins the access.
Thus, the MCF5307 becomes the explicit external bus master. Also during C4, the external
device removes the grant from the MCF5307 by negating BG. As the current bus master,
the MCF5307 continues to assert BD until the current transfer completes. Because BG is
negated, the MCF5307 negates BD during C9 and three-states the external bus, thereby
returning external bus mastership to the external device.
18-26
s
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
Figure 18-27. Two-Wire Bus Arbitration with Bus Request Asserted
BCLKO
D[31:0]
R/W
TIP
BG
BD
AS
TS
TA
Freescale Semiconductor, Inc.
C1
For More Information On This Product,
External Master
C2
Go to: www.freescale.com
MCF5307 User’s Manual
C3
C4
C5
C6
MCF5307
C7
C8
C9