mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 70
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mcf5307cft90b
Manufacturer Part Number
mcf5307cft90b
Description
Mcf5307 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MCF5307CFT90B.pdf
(484 pages)
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Programming Model
Table 2-3 describes SR fields.
2.2.2.2 Vector Base Register (VBR)
The VBR holds the base address of the exception vector table in memory. The displacement
of an exception vector is added to the value in this register to access the vector table.
VBR[19–0] are not implemented and are assumed to be zero, forcing the vector table to be
aligned on a 0-modulo-1-Mbyte boundary.
2.2.2.3 Cache Control Register (CACR)
The CACR controls operation of both the instruction and data cache memory. It includes
bits for enabling, freezing, and invalidating cache contents. It also includes bits for defining
the default cache mode and write-protect fields. See Section 4.10.1, “Cache Control
Register (CACR).”
Rc[11–0]
2-30
Reset
15
13
12
10–8
7–0
Field
Bits
R/W R/W
Reset
Field
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read from
T
S
M
I
CCR
Name
15
T
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Exception vector table base address
—
14
R
0
Trace enable. When T is set, the processor performs a trace exception after every instruction.
Supervisor/user state. Indicates whether the processor is in supervisor or user mode
0 User mode
1 Supervisor mode
Master/interrupt state. Cleared by an interrupt exception. It can be set by software during execution
of the RTE or move to SR instructions so the OS can emulate an interrupt stack pointer.
Interrupt priority mask. Defines the current interrupt priority. Interrupt requests are inhibited for all
priority levels less than or equal to the current priority, except the edge-sensitive level-7 request,
which cannot be masked.
Condition code register. See Table 2-1.
the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
R/W
13
S
1
System byte
R/W
12
M
0
Freescale Semiconductor, Inc.
Figure 2-6. Vector Base Register (VBR)
Table 2-3. Status Field Descriptions
For More Information On This Product,
Figure 2-5. Status Register (SR)
—
11
R
0
0000_0000_0000_0000_0000_0000_0000_0000
Go to: www.freescale.com
10
MCF5307 User’s Manual
R/W
111
9
I
8
Description
0x801
R/W
P
0
7
6
Condition code register (CCR)
00
—
R
5
—
R/W
—
X
4
8
R/W
7
—
N
3
6
R/W
5
—
Z
2
4
R/W
3
—
V
1
2
R/W
1
—
C
0
0
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