mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 16

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Paragraph
Number
17.5.5.3
17.5.6
17.5.7
17.5.8
17.6
17.6.1
17.6.2
17.6.3
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
17.7.7
17.8
17.8.1
17.9
17.9.1
17.9.2
17.9.3
17.9.4
17.10
17.10.1
17.10.2
17.11
17.12
17.12.1
17.12.2
17.13
17.13.1
17.13.2
17.13.3
17.13.4
17.13.5
17.14
17.14.1
17.14.2
17.14.3
17.14.4
17.14.5
xvi
Chip-Select Module Signals ........................................................................... 17-15
DRAM Controller Signals .............................................................................. 17-16
DMA Controller Module Signals.................................................................... 17-17
Serial Module Signals ..................................................................................... 17-18
Timer Module Signals..................................................................................... 17-18
Parallel I/O Port (PP[15:0]) ............................................................................ 17-19
I2C Module Signals ........................................................................................ 17-19
Debug and Test Signals .................................................................................. 17-20
Debug Module/JTAG Signals......................................................................... 17-21
D4—Address Configuration (ADDR_CONFIG) ....................................... 17-14
D[3:2]—Frequency Control PLL (FREQ[1:0] ..........................................) 17-15
D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15
Chip-Select (CS[7:0]) ................................................................................. 17-16
Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16
Output Enable (OE) .................................................................................... 17-16
Row Address Strobes (RAS[1:0])............................................................... 17-16
Column Address Strobes (CAS[3:0]) ......................................................... 17-16
DRAM Write (DRAMW)........................................................................... 17-17
Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17
Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17
Synchronous DRAM Clock Enable (SCKE) .............................................. 17-17
Synchronous Edge Select (EDGESEL) ...................................................... 17-17
DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-18
Transmitter Serial Data Output (TxD)........................................................ 17-18
Receiver Serial Data Input (RxD)............................................................... 17-18
Clear to Send (CTS).................................................................................... 17-18
Request to Send (RTS) ............................................................................... 17-18
Timer Inputs (TIN[1:0]).............................................................................. 17-19
Timer Outputs (TOUT1, TOUT0) .............................................................. 17-19
I2C Serial Clock (SCL)............................................................................... 17-19
I2C Serial Data (SDA)................................................................................ 17-19
Test Mode (MTMOD[3:0]) ........................................................................ 17-20
High Impedance (HIZ)................................................................................ 17-20
Processor Clock Output (PSTCLK)............................................................ 17-20
Debug Data (DDATA[3:0])........................................................................ 17-20
Processor Status (PST[3:0])........................................................................ 17-20
Test Reset/Development Serial Clock (TRST/DSCLK) ............................ 17-21
Test Mode Select/Breakpoint (TMS/BKPT) .............................................. 17-22
Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22
Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22
Test Clock (TCK) ....................................................................................... 17-23
D[6:5]—Port Size Configuration (PS_CONFIG[1:0]) ........................... 17-14
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MCF5307 User’s Manual
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