mcf5307cft90b Freescale Semiconductor, Inc, mcf5307cft90b Datasheet - Page 51

• Manufacturer Part Number: mcf5307cft90b
• Description: Mcf5307 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
ColdFire Module Description
1.3.7.5 JTAG
To help with system diagnostics and manufacturing testing, the MCF5307 processor
includes dedicated user-accessible test logic that complies with the IEEE 1149.1a standard
for boundary-scan testability, often referred to as the Joint Test Action Group, or JTAG. For
more information, refer to the IEEE 1149.1a standard.
1.3.8 System Debug Interface
The ColdFire processor core debug interface is provided to support system debugging in
conjunction with low-cost debug and emulator development tools. Through a standard
debug interface, users can access real-time trace and debug information. This allows the
processor and system to be debugged at full speed without the need for costly in-circuit
emulators. The debug unit in the MCF5307 is a compatible upgrade to the MCF52xx debug
module with added flexibility in the breakpoint registers and a new command to view the
program counter (PC).
The on-chip breakpoint resources include a total of 6 programmable registers—a set of
address registers (with two 32-bit registers), a set of data registers (with a 32-bit data
register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask
register. These registers can be accessed through the dedicated debug serial communication
channel or from the processor’s supervisor mode programming model. The breakpoint
registers can be configured to generate triggers by combining the address, data, and PC
conditions in a variety of single or dual-level definitions. The trigger event can be
programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF5307’s new interrupt servicing options during emulator mode allow real-time
critical interrupt service routines to be serviced while processing a debug interrupt event,
thereby ensuring that the system continues to operate even during debugging.
To support program trace, the Version 3 debug module provides processor status (PST[3:0])
and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide
execution status, captured operand data, and branch target addresses defining processor
activity at the CPU’s clock rate.
1.3.9 PLL Module
The MCF5307 PLL module is shown in Figure 1-3.
Chapter 1. Overview
1-11
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